Compiler Supports and Optimizations for PAC VLIW DSP Processors

The Parallel Architecture Core (PAC) is a new VLIW DSP architecture, featuring a two cluster design, and partitioned, distributed register files with restricted access ports. Such an irregular processor poses many challenges in the construction of its compiler. This paper presents our work in providing the compilation support for PAC, based on the Open Research Compiler (ORC). We describe the design of the PAC processor and code generation methods used in coping with its features. Evaluation results of the compiler/architecture are then given, demonstrating the effectiveness of our presented methods.